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(R)
ISO2-CMOS
MT8870D/MT8870D-1
Integrated DTMF Receiver
Features
* * * * * * * * Complete DTMF Receiver Low power consumption Internal gain setting amplifier Adjustable guard time Central office quality Power-down mode Inhibit mode Backward compatible with MT8870C/MT8870C-1
ISSUE 3
May1995
Ordering Information MT8870DE/DE-1 18 Pin Plastic DIP MT8870DC/DC-1 18 Pin Ceramic DIP MT8870DS/DS-1 18 Pin SOIC MT8870DN/DN-1 20 Pin SSOP MT8870DT/DT-1 20 Pin TSSOP -40 C to +85 C
Description
The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tonepairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.
Applications
* * * * * * * Receiver system for British Telecom (BT) or CEPT Spec (MT8870D-1) Paging systems Repeater systems/mobile radio Credit card systems Remote control Personal computers Telephone answering machine
VDD VSS VRef
INH
PWDN
Bias Circuit
VRef Buffer Q1
Chip Chip Power Bias IN + IN GS Dial Tone Filter
High Group Filter Zero Crossing Detectors Low Group Filter
Digital Detection Algorithm
Code Converter and Latch
Q2
Q3 Q4
to all Chip Clocks
St GT
Steering Logic
OSC1
OSC2
St/GT
ESt
STD
TOE
Figure 1 - Functional Block Diagram
4-11
MT8870D/MT8870D-1
IN+ INGS VRef INH PWDN OSC1 OSC2 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
ISO2-CMOS
VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
IN+ INGS VRef INH PWDN NC OSC1 OSC2 VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD St/GT ESt StD NC Q4 Q3 Q2 Q1 TOE
18 PIN CERDIP/PLASTIC DIP/SOIC
20 PIN SSOP/TSSOP
Figure 2 - Pin Connections
Pin Description
Pin # 18 1 2 3 4 5 6 7 8 9 10 20 1 2 3 4 5 6 8 9 10 11 Name IN+ INGS VRef INH PWDN OSC1 OSC2 VSS TOE Q1-Q4 Non-Inverting Op-Amp (Input). Inverting Op-Amp (Input). Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 6 and Fig. 10). Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. Clock (Input). Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. Ground (Input). 0V typical. Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally. Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (Input). +5V typical. No Connection. Description
11- 1214 15 15 17
StD
16
18
ESt
17
19
St/GT
18
20 7, 16
VDD NC
4-12
ISO2-CMOS
Functional Description
VDD
MT8870D/MT8870D-1
The MT8870D/MT8870D-1 monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Filter Section Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection (see Figure 3). Each filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. Decoder Section Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while
0
VDD St/GT ESt R StD MT8870D/ MT8870D-1
C vc
tGTA=(RC)In(VDD/VTSt) tGTP=(RC)In[VDD/(VDD-VTSt)]
Figure 4 - Basic Steering Circuit providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the "signal condition" in some industry specifications) the "Early Steering" (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state (see "Steering Circuit"). Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 4) to rise as the capacitor discharges. Provided signal
PRECISE DIAL TONES X=350 Hz Y=440 Hz DTMF TONES A=697 Hz B=770 Hz C=852 Hz D=941 Hz E=1209 Hz F=1336 Hz G=1477 Hz H=1633 Hz
10
20 ATTENUATION (dB) 30
40
50
AAAA AA AA A A AA AAA AAAAAAAAAAAAAAAAAA AA AA AAAA A AAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A AAAAAAAAA AAA AAAA AA AAAAAAA AA AAAA AA AAA AAA AA AA AAA AAA AA AA AAAAA AAAAAA AAA AAAA AAA AA AAAAAAA AAA AA AA AAA AAA AAA AA A AAAAA AAAAAA AAA AA AAA AAA AA AAA AAAA AA AAA AAA AA A AA AA AA AA AAA AA AAA AA AA AA AAA AA AAA AA AA AA AAA AA AAA AA AA AAA AA AA AA AAA AA AAA AAA AA A AA AA AA AA AAA AA AAAAAAA AAAAAAAAAA AAAAAAAAAAA AA AAAAAAAAA AAAAA AAA AAA A AAAAAA AAAA AAA AA AAAAA AA AAA AAA AA A AAA AA AA AA AAA AA AA AAA AA AA AA AAA AAAA AA AAA AA AAA AAAA AAA AA AAAAA AAAAA AAAA AA AAA AAA AAA AA AAA AAA AA AAA AAA AA AAA AA AAA AAA AA AAA AA AAA AAA AA A AA AA AA
1kHz X Y AB C D E F G H FREQUENCY (Hz)
Figure 3 - Filter Response
4-13
MT8870D/MT8870D-1
ISO2-CMOS
Digit ANY 1 2 3 4 5 6 7 8 9 0 * # A B C D A TOE L H H H H H H H H H H H H H H H H H H H H INH X X X X X X X X X X X X X L L L L H H H H ESt H H H H H H H H H H H H H H H H H L L L L undetected, the output code will remain the same as the previous detected code Q4 Z 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Q3 Z 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Q2 Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Q1 Z 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (V TSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in Figure 4 is applicable. Component values are chosen according to the formula:
B C D
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON`T CARE
t REC=t DP+tGTP tID=tDA+t GTA
The value of t DP is a device parameter (see Figure 11) and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 F is
tGTP=(RPC1)In[VDD/(VDD-VTSt)]
VDD C1 St/GT R1 ESt R2
recommended for most applications, leaving R to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 5.
tGTA=(R1C1)In(VDD/VTSt) RP=(R1R2)/(R1+R2)
a) decreasing tGTP; (tGTPtGTP=(R1C1)In[VDD/(VDD-VTSt)]
VDD C1 St/GT R2
tGTA=(RPC1)In(VDD/VTSt) RP=(R1R2)/(R 1+R2)
R1 ESt
b) decreasing tGTA; (tGTP>tGTA)
Figure 5 - Guard Time Adjustment
4-14
ISO2-CMOS
Power-down and Inhibit Mode A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1). Differential Input Configuration The input arrangement of the MT8870D/MT8870D-1 provides a differential-input operational amplifier as well as a bias source (VRef) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 10 with the op-amp connected for unity gain and VRef biasing the input at 1/2VDD. Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R 5. Crystal Oscillator
MT8870D/MT8870D-1
C1
R1
IN+
MT8870D/ MT8870D-1 + -
INC2 R4 R5 R3 GS
R2
VRef
Differential Input Amplifier C1=C2=10 nF R1=R4=R 5=100 k All resistors are 1% tolerance. R2=60k, R3=37.5 k All capacitors are 5% tolerance. R3 = R2 R5 R 2+R5 R5 R1
VOLTAGE GAIN (Av diff)= INPUT IMPEDANCE (ZINDIFF) = 2 R1 2 +
1 c
2
Figure 6 - Differential Input Configuration The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is normally connected as shown in Figure 10 (SingleEnded Input Configuration). However, it is possible to configure several MT8870D/MT8870D-1 devices employing only a single oscillator crystal. The oscillator output of the first device in the chain is coupled through a 30 pF capacitor to the oscillator input (OSC1) of the next device. Subsequent devices are connected in a similar fashion. Refer to Figure 7 for details. The problems associated with unbalanced loading are not a concern with the arrangement shown, i.e., precision balancing capacitors are not required.
C X-tal OSC1 OSC2
To OSC1 of next MT8870D/MT8870D-1
OSC2 C
OSC1
C=30 pF X-tal=3.579545 MHz
Figure 7 - Oscillator Connection Parameter R1 L1 C1 C0 Qm f Unit Ohms mH pF pF % Resonator 10.752 .432 4.984 37.915 896.37 0.2%
Table 2. Recommended Resonator Specifications
Note: Qm=quality factor of RLC model, i.e., 1/2R1C1.
4-15
MT8870D/MT8870D-1
Applications
ISO2-CMOS
RECEIVER SYSTEM FOR BRITISH TELECOM SPEC POR 1151 The circuit shown in Fig. 9 illustrates the use of MT8870D-1 device in a typical receiver system. BT Spec defines the input signals less than -34 dBm as the non-operate level. This condition can be attained by choosing a suitable values of R 1 and R 2 to provide 3 dB attenuation, such that -34 dBm input signal will correspond to -37 dBm at the gain setting pin GS of MT8870D-1. As shown in the diagram, the component values of R3 and C2 are the guard time requirements when the total component tolerance is 6%. For better performance, it is recommended to use the non-symmetric guard time circuit in Fig. 8.
tGTP=(RPC1)In[VDD/(VDD-VTSt)] tGTA=(R1C1)In(VDD/VTSt) RP=(R1R2)/(R1+R2)
C1 St/GT
VDD
R1 ESt
R2
Notes: R1=368K 1% R2=2.2M 1% C1=100nF 5%
Figure 8 - Non-Symmetric Guard Time Circuit
VDD C1 DTMF Input C2
R1
MT8870D-1 IN+ INGS VRef INH PWDN OSC 1 OSC 2 VSS VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
R3
R2
X1
NOTES: R1 = 102K 1% R2 = 71.5K 1% R3 = 390K 1 % C1,C2 = 100 nF 5% X1 = 3.579545 MHz 0.1% VDD = 5.0V 5%
Figure 9 - Single-Ended Input Configuration for BT or CEPT Spec
4-16
ISO2-CMOS
Absolute Maximum Ratings
Parameter 1 2 3 4 5 DC Power Supply Voltage Voltage on any pin Current at any pin (other than supply) Storage temperature Package power dissipation Symbol VDD VI II TSTG PD
MT8870D/MT8870D-1
Min
Max 7
Units V V mA C mW
VSS-0.3
VDD+0.3 10
-65
+150 500
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Derate above 75 C at 16 mW / C. All leads soldered to board.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 DC Power Supply Voltage Operating Temperature Crystal/Clock Frequency Crystal/Clock Freq.Tolerance Sym VDD TO fc fc Min 4.75 -40
3.579545
Typ 5.0
Max 5.25 +85
Units V C MHz %
Test Conditions
0.1
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - VDD=5.0V 5%, VSS=0V, -40C TO +85C, unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
O U T P U T S I N P U T S S U P P L Y
Sym IDDQ IDD PO VIH VIL IIH/IIL ISO ISI RIN VTSt VOL VOH IOL IOH VRef ROR
Min
Typ 10 3.0 15
Max 25 9.0
Units A mA mW V
Test Conditions PWDN=VDD
Standby supply current Operating supply current Power consumption High level input Low level input voltage Input leakage current Pull up (source) current Pull down (sink) current Input impedance (IN+, IN-) Steering threshold voltage Low level output voltage High level output voltage Output low (sink) current Output high (source) current VRef output voltage VRef output resistance
fc=3.579545 MHz VDD=5.0V VDD=5.0V VIN=VSS or VDD TOE (pin 10)=0, VDD=5.0V INH=5.0V, PWDN=5.0V, VDD=5.0V @ 1 kHz VDD = 5.0V No load No load VOUT=0.4 V VOUT=4.6 V No load, VDD = 5.0V
3.5 1.5 0.1 7.5 15 10 2.2 2.4 2.5 VSS+0.03 VDD-0.03 1.0 0.4 2.3 2.5 0.8 2.5 1 2.7 20 45
V A A A M V V V mA mA V k
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
4-17
MT8870D/MT8870D-1
Gain Setting Amplifier Characteristics 1 2 3 4 5 6 7 8 9 10 11 Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection DC open loop voltage gain Unity gain bandwidth Output voltage swing Maximum capacitive load (GS) Resistive load (GS) Common mode range
ISO2-CMOS
Operating Characteristics - VDD=5.0V5%, VSS=0V, -40C TO +85C ,unless otherwise stated.
Sym IIN RIN VOS PSRR CMRR AVOL fC VO CL RL VCM 2.5 50 40 32 0.30 4.0 100 50 10 25 Min Typ Max 100 Units nA M mV dB dB dB MHz Vpp pF k Vpp No Load Load 100 k to VSS @ GS 1 kHz 0.75 V VIN 4.25 V biased at VRef =2.5 V Test Conditions VSS VIN VDD
MT8870D AC Electrical Characteristics Characteristics 1 2 3 4 5 6 7 8 Valid input signal levels (each tone of composite signal) Negative twist accept Positive twist accept Frequency deviation accept Frequency deviation reject Third tone tolerance Noise tolerance Dial tone tolerance Sym
VDD =5.0V 5%, VSS=0V, -40C TO +85C , using Test Circuit shown in Figure 10.
Min -29 27.5
Typ
Max +1 869 8 8
Units dBm mVRMS dB dB
Notes* 1,2,3,5,6,9 1,2,3,5,6,9 2,3,6,9,12 2,3,6,9,12 2,3,5,9 2,3,5,9
1.5% 2 Hz 3.5% -16 -12 +22 dB dB dB
2,3,4,5,9,10 2,3,4,5,7,9,10 2,3,4,5,8,9,11
Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all DTMF tones. 3. Tone duration= 40 ms, tone pause= 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by 1.5 % 2 Hz. 7. Bandwidth limited (3 kHz ) Gaussian noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) 2 %. 9. For an error rate of better than 1 in 10,000. 10. Referenced to lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept level. 12. Guaranteed by design and characterization.
4-18
ISO2-CMOS
MT8870D-1 AC Electrical Characteristics Characteristics 1 Valid input signal levels (each tone of composite signal) Input Signal Level Reject Negative twist accept Positive twist accept Frequency deviation accept Frequency deviation reject Third zone tolerance Noise tolerance Dial tone tolerance 1.5% 2 Hz 3.5% -18.5 -12 +22 Sym
MT8870D/MT8870D-1
VDD =5.0V5%, VSS=0V, -40C TO +85C , using Test Circuit shown in Figure 10.
Min -31 21.8 -37 10.9
Typ
Max +1 869
Units dBm mVRMS dBm mVRMS
Notes* Tested at VDD=5.0V 1,2,3,5,6,9 Tested at VDD=5.0V 1,2,3,5,6,9 2,3,6,9,13 2,3,6,9,13 2,3,5,9 2,3,5,9
2 3 4 5 6 7 8 9
8 8
dB dB
dB dB dB
2,3,4,5,9,12 2,3,4,5,7,9,10 2,3,4,5,8,9,11
Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. 1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all DTMF tones. 3. Tone duration= 40 ms, tone pause= 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by 1.5 % 2 Hz. 7. Bandwidth limited (3 kHz ) Gaussian noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) 2 %. 9. For an error rate of better than 1 in 10,000. 10. Referenced to lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept level. 12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz. 13. Guaranteed by design and characterization.
*NOTES
4-19
MT8870D/MT8870D-1
ISO2-CMOS
AC Electrical Characteristics - VDD=5.0V5%, VSS=0V, -40C To +85C , using Test Circuit shown in Figure 10.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
C L O C K O U T P U T S T I M I N G
Sym tDP tDA tREC tREC tID tDO tPQ tPStD tQStD tPTE tPTD tPU tPD fC tLHCL tHLCL DCCL
Min 5 0.5
Typ 11 4
Max 14 8.5 40
Units ms ms ms ms
Conditions Note 1 Note 1 Note 2 Note 2 Note 2 Note 2 TOE=VDD TOE=VDD TOE=VDD load of 10 k, 50 pF load of 10 k, 50 pF Note 3
Tone present detect time Tone absent detect time Tone duration accept Tone duration reject Interdigit pause accept Interdigit pause reject Propagation delay (St to Q) Propagation delay (St to StD) Output data set up (Q to StD) Propagation delay (TOE to Q ENABLE) Propagation delay (TOE to Q DISABLE) Power-up time Power-down time Crystal/clock frequency Clock input rise time Clock input fall time Clock input duty cycle
20 40 20 8 12 3.4 50 300 30 20 3.5759 3.5795 3.5831 110 110 40 50 60 11 16
ms ms s s s ns ns ms ms MHz ns ns % pF
P D W N
Ext. clock Ext. clock Ext. clock
18 Capacitive load (OSC2) CLO 30 Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES: 1. Used for guard-time calculation purposes only. 2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
VDD C1 DTMF Input R1 C2 MT8870D/MT8870D-1 IN+ INR2 GS VRef INH PDWN OSC 1 X-tal OSC 2 VSS VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE NOTES: R1,R2=100K 1% R3=300K 1% C1,C2=100 nF 5% X-tal=3.579545 MHz 0.1% R3
Figure 10 - Single-Ended Input Configuration
4-20
ISO2-CMOS
MT8870D/MT8870D-1
D
EVENTS tREC
A tREC
B
C tID
E tDO TONE #n + 1
F
G
Vin tDP ESt tGTP St/GT tPQ
TONE #n
AA AA AA AA
TONE #n + 1
tDA
tGTA VTSt
tQStD Q1-Q4 DECODED TONE # (n-1) tPSrD StD TOE #n
HIGH IMPEDANCE # (n + 1)
tPTE tPTD
EXPLANATION OF EVENTS A) B) C) D) E) F) G) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED. TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID TONE. OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH IMPEDANCE). ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED. END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE.
EXPLANATION OF SYMBOLS Vin ESt St/GT Q1 -Q 4 StD TOE tREC tREC tID tDO tDP tDA tGTP tGTA DTMF COMPOSITE INPUT SIGNAL. EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. 4-BIT DECODED TONE OUTPUT. DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE. MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION MAXIMUM TIME BETWEEN VALID DTMF SIGNALS. MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL. TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS. TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS. GUARD TIME, TONE PRESENT. GUARD TIME, TONE ABSENT.
Figure 11 - Timing Diagram
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MT8870D/MT8870D-1
NOTES:
ISO2-CMOS
4-22

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